The CPU was faster than the memory by the mid to late 70s (though they did start roughly equal at the start of the decade). You would insert a number of "wait states" with an external counter to ensure your memories' timing was not violated.

At that time RAM was asynchronous, you put an address in the A bus and by the specified delay time you would have your result on the output. Later on memories were pipelined and that is when they got their clock.